# xmpl_trx_rxaack.c - Receiving Frames with RX_AACK

Application Description

Code Example

    /* $Id: xmpl_trx_rxaack.c,v 1.3 2009/12/22 16:47:10 joerg_wunsch Exp $ */
    /* Example for receiving frames in rx_aack mode */

    #include "board.h"
    #include "transceiver.h"
    #include "ioutil.h"
    #include "xmpl.h"

    static volatile bool tx_in_progress;
    static volatile uint8_t tx_cnt;
    static volatile uint8_t tx_fail;

    #define SEQ_OFFSET     (2)
    #define TX_FAIL_OFFSET (7)
    #define TX_SRAM_OFFSET (1)

    int main(void)
    {
    trx_regval_t rval;

        /* This will stop the application before initializing the radio transceiver
         * (ISP issue with MISO pin, see FAQ)
         */
        trap_if_key_pressed();

        /* Step 0: init MCU peripherals */
        LED_INIT();
        trx_io_init(SPI_RATE_1_2);
        LED_SET_VALUE(LED_MAX_VALUE);
        LED_SET_VALUE(0);

        /* Step 1: initialize the transceiver */
        TRX_RESET_LOW();
        TRX_SLPTR_LOW();
        DELAY_US(TRX_RESET_TIME_US);
        TRX_RESET_HIGH();
        trx_reg_write(RG_TRX_STATE,CMD_TRX_OFF);
        DELAY_MS(TRX_INIT_TIME_US);
        rval = trx_bit_read(SR_TRX_STATUS);
        ERR_CHECK(TRX_OFF!=rval);
        LED_SET_VALUE(1);

        /* Step 2: setup transmitter
         * - configure radio channel
         * - enable transmitters automatic crc16 generation
         * - go into RX AACK state,
         * - configure address filter
         * - enable "receive end" IRQ
         */
        trx_bit_write(SR_CHANNEL,CHANNEL);
        trx_bit_write(SR_TX_AUTO_CRC_ON,1);

        trx_reg_write(RG_PAN_ID_0,(PANID&0xff));
        trx_reg_write(RG_PAN_ID_1,(PANID>>8));

        trx_reg_write(RG_SHORT_ADDR_0,(SHORT_ADDR&0xff));
        trx_reg_write(RG_SHORT_ADDR_1,(SHORT_ADDR>>8));

        trx_reg_write(RG_TRX_STATE,CMD_RX_AACK_ON);
    #if defined(TRX_IRQ_TRX_END)
        trx_reg_write(RG_IRQ_MASK,TRX_IRQ_TRX_END);
    #elif defined(TRX_IRQ_RX_END)
        trx_reg_write(RG_IRQ_MASK,TRX_IRQ_RX_END);
    #else
    #  error "Unknown IRQ bits"
    #endif
        sei();
        LED_SET_VALUE(2);

        /* Step 3: send a frame each 500ms */
        tx_cnt = 0;
        tx_in_progress = false;
        LED_SET_VALUE(0);

        while(1);

    }

    #if defined(TRX_IF_RFA1)
    ISR(TRX24_RX_END_vect)
    {
    static volatile trx_regval_t trac_status;

        trac_status = trx_bit_read(SR_TRAC_STATUS);

        LED_TOGGLE(0);
        if (trac_status != TRAC_SUCCESS)
        {
            LED_TOGGLE(1);
        }
    }
    #else  /* !RFA1 */
    ISR(TRX_IRQ_vect)
    {
    static volatile trx_regval_t irq_cause;
    static volatile trx_regval_t trac_status;

        irq_cause = trx_reg_read(RG_IRQ_STATUS);
        trac_status = trx_bit_read(SR_TRAC_STATUS);

        if (irq_cause & TRX_IRQ_TRX_END)
        {
            LED_TOGGLE(0);
            if (trac_status != TRAC_SUCCESS)
            {
                LED_TOGGLE(1);
            }
        }
    }
    #endif  /* RFA1 */

    /* EOF */