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at86rf232.h
1 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf232.txt */
2
3 /* Copyright (c) 2011 Axel Wachtler
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
8 are met:
9
10 * Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15 * Neither the name of the authors nor the names of its contributors
16 may be used to endorse or promote products derived from this software
17 without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE. */
30
31 /* $Id$ */
36 #ifndef AT86RF232_H
37 #define AT86RF232_H (1)
38
39 /* === Includes ============================================================== */
40
41 /* === Externals ============================================================= */
42
43 /* === Types ================================================================= */
44
45 typedef uint8_t trx_ramaddr_t;
46 typedef uint8_t trx_regval_t;
47 typedef uint8_t trx_regaddr_t;
48
49 /* === Macros ================================================================ */
51 #define RG_TRX_STATUS (0x1)
52
53 #define SR_CCA_DONE 0x1,0x80,7
54
55 #define SR_CCA_STATUS 0x1,0x40,6
56
57 #define SR_TRX_STATUS 0x1,0x1f,0
58 #ifndef P_ON
59 #define P_ON (0)
60 #endif /* P_ON */
61 #ifndef BUSY_RX
62 #define BUSY_RX (1)
63 #endif /* BUSY_RX */
64 #ifndef BUSY_TX
65 #define BUSY_TX (2)
66 #endif /* BUSY_TX */
67 #ifndef RX_ON
68 #define RX_ON (6)
69 #endif /* RX_ON */
70 #ifndef TRX_OFF
71 #define TRX_OFF (8)
72 #endif /* TRX_OFF */
73 #ifndef PLL_ON
74 #define PLL_ON (9)
75 #endif /* PLL_ON */
76 #ifndef TRX_SLEEP
77 #define TRX_SLEEP (15)
78 #endif /* TRX_SLEEP */
79 #ifndef BUSY_RX_AACK
80 #define BUSY_RX_AACK (17)
81 #endif /* BUSY_RX_AACK */
82 #ifndef BUSY_TX_ARET
83 #define BUSY_TX_ARET (18)
84 #endif /* BUSY_TX_ARET */
85 #ifndef RX_AACK_ON
86 #define RX_AACK_ON (22)
87 #endif /* RX_AACK_ON */
88 #ifndef TX_ARET_ON
89 #define TX_ARET_ON (25)
90 #endif /* TX_ARET_ON */
91 #ifndef RX_ON_NOCLK
92 #define RX_ON_NOCLK (28)
93 #endif /* RX_ON_NOCLK */
94 #ifndef RX_AACK_ON_NOCLK
95 #define RX_AACK_ON_NOCLK (29)
96 #endif /* RX_AACK_ON_NOCLK */
97 #ifndef BUSY_RX_AACK_NOCLK
98 #define BUSY_RX_AACK_NOCLK (30)
99 #endif /* BUSY_RX_AACK_NOCLK */
100
101 #define RG_TRX_STATE (0x2)
102
103 #define SR_TRAC_STATUS 0x2,0xe0,5
104 #ifndef TRAC_SUCCESS
105 #define TRAC_SUCCESS (0)
106 #endif /* TRAC_SUCCESS */
107 #ifndef TRAC_SUCCESS_DATA_PENDING
108 #define TRAC_SUCCESS_DATA_PENDING (1)
109 #endif /* TRAC_SUCCESS_DATA_PENDING */
110 #ifndef TRAC_SUCCESS_WAIT_FOR_ACK
111 #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
112 #endif /* TRAC_SUCCESS_WAIT_FOR_ACK */
113 #ifndef TRAC_CHANNEL_ACCESS_FAILURE
114 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
115 #endif /* TRAC_CHANNEL_ACCESS_FAILURE */
116 #ifndef TRAC_NO_ACK
117 #define TRAC_NO_ACK (5)
118 #endif /* TRAC_NO_ACK */
119 #ifndef TRAC_INVALID
120 #define TRAC_INVALID (7)
121 #endif /* TRAC_INVALID */
122
123 #define SR_TRX_CMD 0x2,0x1f,0
124 #ifndef CMD_NOP
125 #define CMD_NOP (0)
126 #endif /* CMD_NOP */
127 #ifndef CMD_TX_START
128 #define CMD_TX_START (2)
129 #endif /* CMD_TX_START */
130 #ifndef CMD_FORCE_TRX_OFF
131 #define CMD_FORCE_TRX_OFF (3)
132 #endif /* CMD_FORCE_TRX_OFF */
133 #ifndef CMD_RX_ON
134 #define CMD_RX_ON (6)
135 #endif /* CMD_RX_ON */
136 #ifndef CMD_TRX_OFF
137 #define CMD_TRX_OFF (8)
138 #endif /* CMD_TRX_OFF */
139 #ifndef CMD_PLL_ON
140 #define CMD_PLL_ON (9)
141 #endif /* CMD_PLL_ON */
142 #ifndef CMD_RX_AACK_ON
143 #define CMD_RX_AACK_ON (22)
144 #endif /* CMD_RX_AACK_ON */
145 #ifndef CMD_TX_ARET_ON
146 #define CMD_TX_ARET_ON (25)
147 #endif /* CMD_TX_ARET_ON */
148
149 #define RG_TRX_CTRL_0 (0x3)
150
151 #define SR_CLKM_SHA_SEL 0x3,0x8,3
152
153 #define SR_CLKM_CTRL 0x3,0x7,0
154 #ifndef CLKM_no_clock
155 #define CLKM_no_clock (0)
156 #endif /* CLKM_no_clock */
157 #ifndef CLKM_1MHz
158 #define CLKM_1MHz (1)
159 #endif /* CLKM_1MHz */
160 #ifndef CLKM_2MHz
161 #define CLKM_2MHz (2)
162 #endif /* CLKM_2MHz */
163 #ifndef CLKM_4MHz
164 #define CLKM_4MHz (3)
165 #endif /* CLKM_4MHz */
166 #ifndef CLKM_8MHz
167 #define CLKM_8MHz (4)
168 #endif /* CLKM_8MHz */
169 #ifndef CLKM_16MHz
170 #define CLKM_16MHz (5)
171 #endif /* CLKM_16MHz */
172
173 #define RG_TRX_CTRL_1 (0x4)
174
175 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
176
177 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
178
179 #define SR_RX_BL_CTRL 0x4,0x10,4
180
181 #define SR_SPI_CMD_MODE 0x4,0xc,2
182
183 #define SR_IRQ_POLARITY 0x4,0x1,0
184
185 #define SR_IRQ_MASK_MODE 0x4,0x2,1
186
187 #define RG_PHY_TX_PWR (0x5)
188
189 #define SR_TX_PWR 0x5,0xf,0
190
191 #define RG_PHY_RSSI (0x6)
192
193 #define SR_RX_CRC_VALID 0x6,0x80,7
194
195 #define SR_RND_VALUE 0x6,0x60,5
196
197 #define SR_RSSI 0x6,0x1f,0
198
199 #define RG_PHY_ED_LEVEL (0x7)
200
201 #define SR_ED_LEVEL 0x7,0xff,0
202
203 #define RG_PHY_CC_CCA (0x8)
204
205 #define SR_CCA_REQUEST 0x8,0x80,7
206
207 #define SR_CCA_MODE 0x8,0x60,5
208
209 #define SR_CHANNEL 0x8,0x1f,0
210
211 #define RG_CCA_THRES (0x9)
212
213 #define SR_CCA_ED_THRES 0x9,0xf,0
214
215 #define RG_RX_CTRL (0xa)
216
217 #define SR_PDT_THRES 0xa,0xf,0
218
219 #define RG_TRX_CTRL_2 (0xc)
220
221 #define SR_RX_SAFE_MODE 0xc,0x80,7
222
223 #define RG_ANT_DIV (0xd)
224
225 #define SR_ANT_SEL 0xd,0x80,7
226
227 #define SR_ANT_DIV_EN 0xd,0x8,3
228
229 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
230
231 #define SR_ANT_CTRL 0xd,0x3,0
232
233 #define RG_IRQ_MASK (0xe)
234
235 #define SR_MASK_BAT_LOW 0xe,0x80,7
236
237 #define SR_MASK_TRX_UR 0xe,0x40,6
238
239 #define SR_MASK_AMI 0xe,0x20,5
240
241 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
242
243 #define SR_MASK_TRX_END 0xe,0x8,3
244
245 #define SR_MASK_TRX_START 0xe,0x4,2
246
247 #define SR_MASK_PLL_LOCK 0xe,0x1,0
248
249 #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
250
251 #define RG_IRQ_STATUS (0xf)
252
253 #define SR_BAT_LOW 0xf,0x80,7
254
255 #define SR_TRX_UR 0xf,0x40,6
256
257 #define SR_AMI 0xf,0x20,5
258
259 #define SR_CCA_ED_READY 0xf,0x10,4
260
261 #define SR_RX_END 0xf,0x8,3
262
263 #define SR_RX_START 0xf,0x4,2
264
265 #define SR_PLL_LOCK 0xf,0x1,0
266
267 #define SR_PLL_UNLOCK 0xf,0x2,1
268
269 #define RG_VREG_CTRL (0x10)
270
271 #define SR_AVREG_EXT 0x10,0x80,7
272
273 #define SR_AVDD_OK 0x10,0x40,6
274
275 #define SR_DVREG_EXT 0x10,0x8,3
276
277 #define SR_DVDD_OK 0x10,0x4,2
278
279 #define RG_BATMON (0x11)
280
281 #define SR_BATMON_OK 0x11,0x20,5
282
283 #define SR_BATMON_HR 0x11,0x10,4
284
285 #define SR_BATMON_VTH 0x11,0xf,0
286
287 #define RG_XOSC_CTRL (0x12)
288
289 #define SR_XTAL_MODE 0x12,0xf0,4
290
291 #define SR_XTAL_TRIM 0x12,0xf,0
292
293 #define RG_RX_SYN (0x15)
294
295 #define SR_RX_PDT_DIS 0x15,0x80,7
296
297 #define SR_RX_PDT_LEVEL 0x15,0xf,0
298
299 #define RG_XAH_CTRL_1 (0x17)
300
301 #define SR_ARET_TX_TS 0x17,0x80,7
302
303 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
304
305 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
306
307 #define SR_AACK_ACK_TIME 0x17,0x4,2
308
309 #define SR_AACK_PROM_MODE 0x17,0x2,1
310
311 #define RG_FTN_CTRL (0x18)
312
313 #define SR_FTN_START 0x18,0x80,7
314
315 #define RG_XAH_CTRL_2 (0x19)
316
317 #define SR_ARET_FRAME_RETRIES 0x19,0xf0,4
318
319 #define SR_ARET_CSMA_RETRIES 0x19,0xe,1
320
321 #define RG_PLL_CF (0x1a)
322
323 #define SR_PLL_CF_START 0x1a,0x80,7
324
325 #define SR_PLL_CF 0x1a,0xf,0
326
327 #define RG_PLL_DCU (0x1b)
328
329 #define SR_PLL_DCU_START 0x1b,0x80,7
330
331 #define RG_PART_NUM (0x1c)
332
333 #define SR_PART_NUM 0x1c,0xff,0
334 #ifndef RF232_PART_NUM
335 #define RF232_PART_NUM (10)
336 #endif /* RF232_PART_NUM */
337
338 #define RG_VERSION_NUM (0x1d)
339
340 #define SR_VERSION_NUM 0x1d,0xff,0
341 #ifndef RF232_VERSION_NUM
342 #define RF232_VERSION_NUM (2)
343 #endif /* RF232_VERSION_NUM */
344
345 #define RG_MAN_ID_0 (0x1e)
346
347 #define SR_MAN_ID_0 0x1e,0xff,0
348
349 #define RG_MAN_ID_1 (0x1f)
350
351 #define SR_MAN_ID_1 0x1f,0xff,0
352
353 #define RG_SHORT_ADDR_0 (0x20)
354
355 #define SR_SHORT_ADDR_0 0x20,0xff,0
356
357 #define RG_SHORT_ADDR_1 (0x21)
358
359 #define SR_SHORT_ADDR_1 0x21,0xff,0
360
361 #define RG_PAN_ID_0 (0x22)
362
363 #define SR_PAN_ID_0 0x22,0xff,0
364
365 #define RG_PAN_ID_1 (0x23)
366
367 #define SR_PAN_ID_1 0x23,0xff,0
368
369 #define RG_IEEE_ADDR_0 (0x24)
370
371 #define SR_IEEE_ADDR_0 0x24,0xff,0
372
373 #define RG_IEEE_ADDR_1 (0x25)
374
375 #define SR_IEEE_ADDR_1 0x25,0xff,0
376
377 #define RG_IEEE_ADDR_2 (0x26)
378
379 #define SR_IEEE_ADDR_2 0x26,0xff,0
380
381 #define RG_IEEE_ADDR_3 (0x27)
382
383 #define SR_IEEE_ADDR_3 0x27,0xff,0
384
385 #define RG_IEEE_ADDR_4 (0x28)
386
387 #define SR_IEEE_ADDR_4 0x28,0xff,0
388
389 #define RG_IEEE_ADDR_5 (0x29)
390
391 #define SR_IEEE_ADDR_5 0x29,0xff,0
392
393 #define RG_IEEE_ADDR_6 (0x2a)
394
395 #define SR_IEEE_ADDR_6 0x2a,0xff,0
396
397 #define RG_IEEE_ADDR_7 (0x2b)
398
399 #define SR_IEEE_ADDR_7 0x2b,0xff,0
400
401 #define RG_XAH_CTRL_0 (0x2c)
402
403 #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
404
405 #define SR_SLOTTED_OPERATION 0x2c,0x1,0
406
407 #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
408
409 #define RG_CSMA_SEED_0 (0x2d)
410
411 #define SR_CSMA_SEED_0 0x2d,0xff,0
412
413 #define RG_CSMA_SEED_1 (0x2e)
414
415 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
416
417 #define SR_AACK_SET_PD 0x2e,0x20,5
418
419 #define SR_AACK_DIS_ACK 0x2e,0x10,4
420
421 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
422
423 #define SR_CSMA_SEED_1 0x2e,0x7,0
424
425 #define RG_CSMA_BE (0x2f)
426
427 #define SR_MAX_BE 0x2f,0xf0,4
428
429 #define SR_MIN_BE 0x2f,0xf,0
430
431 #define RG_TST_CTRL_DIGI (0x36)
432
433 #define SR_TST_CTRL_DIG 0x36,0xf,0
434
435 #define RADIO_NAME "AT86RF232"
436
437 #define RADIO_PART_NUM (RF232_PART_NUM)
438
439 #define RADIO_VERSION_NUM (RF232_VERSION_NUM)
440
442 #define TRX_CMD_RW (_BV(7) | _BV(6))
443
444 #define TRX_CMD_RR (_BV(7))
445
446 #define TRX_CMD_FW (_BV(6) | _BV(5))
447
448 #define TRX_CMD_FR (_BV(5))
449
450 #define TRX_CMD_SW (_BV(6))
451
452 #define TRX_CMD_SR (0)
453
454 #define TRX_CMD_RADDR_MASK (0x3f)
455
457 #define TRX_RESET_TIME_US (6)
458
460 #define TRX_INIT_TIME_US (510)
461
463 #define TRX_PLL_LOCK_TIME_US (180)
464
465
467 #define TRX_CCA_TIME_US (140)
468
470 #define TRX_IRQ_PLL_LOCK _BV(0)
471
473 #define TRX_IRQ_PLL_UNLOCK _BV(1)
474
476 #define TRX_IRQ_RX_START _BV(2)
477
479 #define TRX_IRQ_TRX_END _BV(3)
480
482 #define TRX_IRQ_CCA_ED _BV(4)
483
485 #define TRX_IRQ_AMI _BV(5)
486
488 #define TRX_IRQ_UR _BV(6)
489
491 #define TRX_IRQ_BAT_LOW _BV(7)
492
494 #define TRAC_SUCCESS (0)
495
496 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
497
498 #define TRAC_NO_ACK (5)
499
500
502 #define TRX_MIN_CHANNEL (11)
503
505 #define TRX_MAX_CHANNEL (26)
506
508 #define TRX_NB_CHANNELS (16)
509
514 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
515
516 #define TRX_SUPPORTS_BAND_2400 (1)
517
521 #define TRX_SUPPORTED_PAGES (42)
522
524 #define TRX_OQPSK250 (0)
525
527 #define TRX_OQPSK500 (1)
528
530 #define TRX_OQPSK1000 (2)
531
533 #define TRX_OQPSK2000 (3)
534
536 #define TRX_NONE (255)
537
538 #endif /* ifndef AT86RF232_H */
trx_regaddr_t
uint8_t trx_regaddr_t
Definition: transceiver.h:89
trx_regval_t
uint8_t trx_regval_t
Definition: transceiver.h:85
trx_ramaddr_t
uint8_t trx_ramaddr_t
Definition: transceiver.h:81