µracoli Manual Version foo

- µracoli
- User Guide
- Reference Guide

at86rf212.h
1 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf212.txt */
2
3 /* Copyright (c) 2008 Axel Wachtler
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
8 are met:
9
10 * Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15 * Neither the name of the authors nor the names of its contributors
16 may be used to endorse or promote products derived from this software
17 without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE. */
30
31 /* $Id$ */
36 #ifndef AT86RF212_H
37 #define AT86RF212_H (1)
38 /* === Includes ============================================================== */
39
40 /* === Externals ============================================================= */
41
42 /* === Types ================================================================= */
43
44 typedef uint8_t trx_ramaddr_t;
45 typedef uint8_t trx_regval_t;
46 typedef uint8_t trx_regaddr_t;
47
48 /* === Macros ================================================================ */
50 #define RG_TRX_STATUS (0x1)
51
52 #define SR_CCA_DONE 0x1,0x80,7
53
54 #define SR_CCA_STATUS 0x1,0x40,6
55
56 #define SR_TRX_STATUS 0x1,0x1f,0
57 #ifndef P_ON
58 #define P_ON (0)
59 #endif /* P_ON */
60 #ifndef BUSY_RX
61 #define BUSY_RX (1)
62 #endif /* BUSY_RX */
63 #ifndef BUSY_TX
64 #define BUSY_TX (2)
65 #endif /* BUSY_TX */
66 #ifndef RX_ON
67 #define RX_ON (6)
68 #endif /* RX_ON */
69 #ifndef TRX_OFF
70 #define TRX_OFF (8)
71 #endif /* TRX_OFF */
72 #ifndef PLL_ON
73 #define PLL_ON (9)
74 #endif /* PLL_ON */
75 #ifndef TRX_SLEEP
76 #define TRX_SLEEP (15)
77 #endif /* TRX_SLEEP */
78 #ifndef BUSY_RX_AACK
79 #define BUSY_RX_AACK (17)
80 #endif /* BUSY_RX_AACK */
81 #ifndef BUSY_TX_ARET
82 #define BUSY_TX_ARET (18)
83 #endif /* BUSY_TX_ARET */
84 #ifndef RX_AACK_ON
85 #define RX_AACK_ON (22)
86 #endif /* RX_AACK_ON */
87 #ifndef TX_ARET_ON
88 #define TX_ARET_ON (25)
89 #endif /* TX_ARET_ON */
90 #ifndef RX_ON_NOCLK
91 #define RX_ON_NOCLK (28)
92 #endif /* RX_ON_NOCLK */
93 #ifndef RX_AACK_ON_NOCLK
94 #define RX_AACK_ON_NOCLK (29)
95 #endif /* RX_AACK_ON_NOCLK */
96 #ifndef BUSY_RX_AACK_NOCLK
97 #define BUSY_RX_AACK_NOCLK (30)
98 #endif /* BUSY_RX_AACK_NOCLK */
99
100 #define RG_TRX_STATE (0x2)
101
102 #define SR_TRAC_STATUS 0x2,0xe0,5
103 #ifndef TRAC_SUCCESS
104 #define TRAC_SUCCESS (0)
105 #endif /* TRAC_SUCCESS */
106 #ifndef TRAC_SUCCESS_DATA_PENDING
107 #define TRAC_SUCCESS_DATA_PENDING (1)
108 #endif /* TRAC_SUCCESS_DATA_PENDING */
109 #ifndef TRAC_SUCCESS_WAIT_FOR_ACK
110 #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
111 #endif /* TRAC_SUCCESS_WAIT_FOR_ACK */
112 #ifndef TRAC_CHANNEL_ACCESS_FAILURE
113 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
114 #endif /* TRAC_CHANNEL_ACCESS_FAILURE */
115 #ifndef TRAC_NO_ACK
116 #define TRAC_NO_ACK (5)
117 #endif /* TRAC_NO_ACK */
118 #ifndef TRAC_INVALID
119 #define TRAC_INVALID (7)
120 #endif /* TRAC_INVALID */
121
122 #define SR_TRX_CMD 0x2,0x1f,0
123 #ifndef CMD_NOP
124 #define CMD_NOP (0)
125 #endif /* CMD_NOP */
126 #ifndef CMD_TX_START
127 #define CMD_TX_START (2)
128 #endif /* CMD_TX_START */
129 #ifndef CMD_FORCE_TRX_OFF
130 #define CMD_FORCE_TRX_OFF (3)
131 #endif /* CMD_FORCE_TRX_OFF */
132 #ifndef CMD_RX_ON
133 #define CMD_RX_ON (6)
134 #endif /* CMD_RX_ON */
135 #ifndef CMD_TRX_OFF
136 #define CMD_TRX_OFF (8)
137 #endif /* CMD_TRX_OFF */
138 #ifndef CMD_PLL_ON
139 #define CMD_PLL_ON (9)
140 #endif /* CMD_PLL_ON */
141 #ifndef CMD_RX_AACK_ON
142 #define CMD_RX_AACK_ON (22)
143 #endif /* CMD_RX_AACK_ON */
144 #ifndef CMD_TX_ARET_ON
145 #define CMD_TX_ARET_ON (25)
146 #endif /* CMD_TX_ARET_ON */
147
148 #define RG_TRX_CTRL_0 (0x3)
149
150 #define SR_PAD_IO 0x3,0xc0,6
151
152 #define SR_PAD_IO_CLKM 0x3,0x30,4
153 #ifndef CLKM_2mA
154 #define CLKM_2mA (0)
155 #endif /* CLKM_2mA */
156 #ifndef CLKM_4mA
157 #define CLKM_4mA (1)
158 #endif /* CLKM_4mA */
159 #ifndef CLKM_6mA
160 #define CLKM_6mA (2)
161 #endif /* CLKM_6mA */
162 #ifndef CLKM_8mA
163 #define CLKM_8mA (3)
164 #endif /* CLKM_8mA */
165
166 #define SR_CLKM_SHA_SEL 0x3,0x8,3
167
168 #define SR_CLKM_CTRL 0x3,0x7,0
169 #ifndef CLKM_no_clock
170 #define CLKM_no_clock (0)
171 #endif /* CLKM_no_clock */
172 #ifndef CLKM_1MHz
173 #define CLKM_1MHz (1)
174 #endif /* CLKM_1MHz */
175 #ifndef CLKM_2MHz
176 #define CLKM_2MHz (2)
177 #endif /* CLKM_2MHz */
178 #ifndef CLKM_4MHz
179 #define CLKM_4MHz (3)
180 #endif /* CLKM_4MHz */
181 #ifndef CLKM_8MHz
182 #define CLKM_8MHz (4)
183 #endif /* CLKM_8MHz */
184 #ifndef CLKM_16MHz
185 #define CLKM_16MHz (5)
186 #endif /* CLKM_16MHz */
187
188 #define RG_TRX_CTRL_1 (0x4)
189
190 #define SR_PA_EXT_EN 0x4,0x80,7
191
192 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
193
194 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
195
196 #define SR_RX_BL_CTRL 0x4,0x10,4
197
198 #define SR_SPI_CMD_MODE 0x4,0xc,2
199
200 #define SR_IRQ_POLARITY 0x4,0x1,0
201
202 #define SR_IRQ_MASK_MODE 0x4,0x2,1
203
204 #define RG_PHY_TX_PWR (0x5)
205
206 #define SR_PA_BOOST 0x5,0x80,7
207
208 #define SR_GC_PA 0x5,0x60,5
209
210 #define SR_TX_PWR 0x5,0x1f,0
211
212 #define RG_PHY_RSSI (0x6)
213
214 #define SR_RX_CRC_VALID 0x6,0x80,7
215
216 #define SR_RND_VALUE 0x6,0x60,5
217
218 #define SR_RSSI 0x6,0x1f,0
219
220 #define RG_PHY_ED_LEVEL (0x7)
221
222 #define SR_ED_LEVEL 0x7,0xff,0
223
224 #define RG_PHY_CC_CCA (0x8)
225
226 #define SR_CCA_REQUEST 0x8,0x80,7
227
228 #define SR_CCA_MODE 0x8,0x60,5
229
230 #define SR_CHANNEL 0x8,0x1f,0
231
232 #define RG_CCA_THRES (0x9)
233
234 #define SR_CCA_ED_THRES 0x9,0xf,0
235
236 #define RG_SFD_VALUE (0xb)
237
238 #define SR_SFD_VALUE 0xb,0xff,0
239
240 #define RG_TRX_CTRL_2 (0xc)
241
242 #define SR_RX_SAFE_MODE 0xc,0x80,7
243
244 #define SR_TRX_OFF_AVDD_EN 0xc,0x40,6
245
246 #define SR_BPSK_OQPSK 0xc,0x8,3
247
248 #define SR_SUB_MODE 0xc,0x4,2
249
250 #define SR_OQPSK_DATA_RATE 0xc,0x3,0
251
252 #define RG_ANT_DIV (0xd)
253
254 #define SR_ANT_SEL 0xd,0x80,7
255
256 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
257
258 #define SR_ANT_CTRL 0xd,0x3,0
259
260 #define RG_IRQ_MASK (0xe)
261
262 #define SR_MASK_BAT_LOW 0xe,0x80,7
263
264 #define SR_MASK_TRX_UR 0xe,0x40,6
265
266 #define SR_MASK_AMI 0xe,0x20,5
267
268 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
269
270 #define SR_MASK_TRX_END 0xe,0x8,3
271
272 #define SR_MASK_RX_START 0xe,0x4,2
273
274 #define SR_MASK_PLL_LOCK 0xe,0x1,0
275
276 #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
277
278 #define RG_IRQ_STATUS (0xf)
279
280 #define SR_BAT_LOW 0xf,0x80,7
281
282 #define SR_TRX_UR 0xf,0x40,6
283
284 #define SR_AMI 0xf,0x20,5
285
286 #define SR_CCA_ED_READY 0xf,0x10,4
287
288 #define SR_TRX_END 0xf,0x8,3
289
290 #define SR_RX_START 0xf,0x4,2
291
292 #define SR_PLL_LOCK 0xf,0x1,0
293
294 #define SR_PLL_UNLOCK 0xf,0x2,1
295
296 #define RG_VREG_CTRL (0x10)
297
298 #define SR_AVREG_EXT 0x10,0x80,7
299
300 #define SR_AVDD_OK 0x10,0x40,6
301
302 #define SR_DVREG_EXT 0x10,0x8,3
303
304 #define SR_DVDD_OK 0x10,0x4,2
305
306 #define RG_BATMON (0x11)
307
308 #define SR_BATMON_OK 0x11,0x20,5
309
310 #define SR_BATMON_HR 0x11,0x10,4
311
312 #define SR_BATMON_VTH 0x11,0xf,0
313
314 #define RG_XOSC_CTRL (0x12)
315
316 #define SR_XTAL_MODE 0x12,0xf0,4
317
318 #define SR_XTAL_TRIM 0x12,0xf,0
319
320 #define RG_CC_CTRL_0 (0x13)
321
322 #define SR_CC_NUMBER 0x13,0xff,0
323
324 #define RG_CC_CTRL_1 (0x14)
325
326 #define SR_CC_BAND 0x14,0x4,2
327
328 #define SR_BAND 0x14,0x1,0
329
330 #define SR_CC_ 0x14,0x2,1
331
332 #define RG_RX_SYN (0x15)
333
334 #define SR_RX_PDT_DIS 0x15,0x80,7
335
336 #define SR_RX_PDT_LEVEL 0x15,0xf,0
337
338 #define RG_RF_CTRL_0 (0x16)
339
340 #define SR_PA_LT 0x16,0xc0,6
341
342 #define SR_GC_TX_OFFS 0x16,0x3,0
343
344 #define RG_XAH_CTRL_1 (0x17)
345
346 #define SR_CSMA_LBT_MODE 0x17,0x80,7
347
348 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
349
350 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
351
352 #define SR_AACK_ACK_TIME 0x17,0x4,2
353
354 #define SR_AACK_PROM_MODE 0x17,0x2,1
355
356 #define RG_FTN_CTRL (0x18)
357
358 #define SR_FTN_START 0x18,0x80,7
359
360 #define RG_RF_CTRL_1 (0x19)
361
362 #define SR_RF_MC 0x19,0xf0,4
363
364 #define RG_PLL_CF (0x1a)
365
366 #define SR_PLL_CF_START 0x1a,0x80,7
367
368 #define RG_PLL_DCU (0x1b)
369
370 #define SR_PLL_DCU_START 0x1b,0x80,7
371
372 #define RG_PART_NUM (0x1c)
373
374 #define SR_PART_NUM 0x1c,0xff,0
375 #ifndef RF212A_PART_NUM
376 #define RF212A_PART_NUM (7)
377 #endif /* RF212A_PART_NUM */
378
379 #define RG_VERSION_NUM (0x1d)
380
381 #define SR_VERSION_NUM 0x1d,0xff,0
382 #ifndef RF212A_VERSION_NUM
383 #define RF212A_VERSION_NUM (1)
384 #endif /* RF212A_VERSION_NUM */
385
386 #define RG_MAN_ID_0 (0x1e)
387
388 #define SR_MAN_ID_0 0x1e,0xff,0
389
390 #define RG_MAN_ID_1 (0x1f)
391
392 #define SR_MAN_ID_1 0x1f,0xff,0
393
394 #define RG_SHORT_ADDR_0 (0x20)
395
396 #define SR_SHORT_ADDR_0 0x20,0xff,0
397
398 #define RG_SHORT_ADDR_1 (0x21)
399
400 #define SR_SHORT_ADDR_1 0x21,0xff,0
401
402 #define RG_PAN_ID_0 (0x22)
403
404 #define SR_PAN_ID_0 0x22,0xff,0
405
406 #define RG_PAN_ID_1 (0x23)
407
408 #define SR_PAN_ID_1 0x23,0xff,0
409
410 #define RG_IEEE_ADDR_0 (0x24)
411
412 #define SR_IEEE_ADDR_0 0x24,0xff,0
413
414 #define RG_IEEE_ADDR_1 (0x25)
415
416 #define SR_IEEE_ADDR_1 0x25,0xff,0
417
418 #define RG_IEEE_ADDR_2 (0x26)
419
420 #define SR_IEEE_ADDR_2 0x26,0xff,0
421
422 #define RG_IEEE_ADDR_3 (0x27)
423
424 #define SR_IEEE_ADDR_3 0x27,0xff,0
425
426 #define RG_IEEE_ADDR_4 (0x28)
427
428 #define SR_IEEE_ADDR_4 0x28,0xff,0
429
430 #define RG_IEEE_ADDR_5 (0x29)
431
432 #define SR_IEEE_ADDR_5 0x29,0xff,0
433
434 #define RG_IEEE_ADDR_6 (0x2a)
435
436 #define SR_IEEE_ADDR_6 0x2a,0xff,0
437
438 #define RG_IEEE_ADDR_7 (0x2b)
439
440 #define SR_IEEE_ADDR_7 0x2b,0xff,0
441
442 #define RG_XAH_CTRL_0 (0x2c)
443
444 #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
445
446 #define SR_SLOTTED_OPERATION 0x2c,0x1,0
447
448 #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
449
450 #define RG_CSMA_SEED_0 (0x2d)
451
452 #define SR_CSMA_SEED_0 0x2d,0xff,0
453
454 #define RG_CSMA_SEED_1 (0x2e)
455
456 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
457
458 #define SR_AACK_SET_PD 0x2e,0x20,5
459
460 #define SR_AACK_DIS_ACK 0x2e,0x10,4
461
462 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
463
464 #define SR_CSMA_SEED_1 0x2e,0x7,0
465
466 #define RG_CSMA_BE (0x2f)
467
468 #define SR_MAX_BE 0x2f,0xf0,4
469
470 #define SR_MIN_BE 0x2f,0xf,0
471
472 #define RADIO_NAME "AT86RF212"
473
474 #define RADIO_PART_NUM (RF212A_PART_NUM)
475
476 #define RADIO_VERSION_NUM (RF212A_VERSION_NUM)
477
479 #define TRX_CMD_RW (_BV(7) | _BV(6))
480
481 #define TRX_CMD_RR (_BV(7))
482
483 #define TRX_CMD_FW (_BV(6) | _BV(5))
484
485 #define TRX_CMD_FR (_BV(5))
486
487 #define TRX_CMD_SW (_BV(6))
488
489 #define TRX_CMD_SR (0)
490
491 #define TRX_CMD_RADDR_MASK (0x3f)
492
494 #define TRX_RESET_TIME_US (6)
495
497 #define TRX_INIT_TIME_US (510)
498
500 #define TRX_PLL_LOCK_TIME_US (180)
501
502
504 #define TRX_CCA_TIME_US (140)
505
507 #define TRX_IRQ_PLL_LOCK _BV(0)
508
510 #define TRX_IRQ_PLL_UNLOCK _BV(1)
511
513 #define TRX_IRQ_RX_START _BV(2)
514
516 #define TRX_IRQ_TRX_END _BV(3)
517
519 #define TRX_IRQ_CCA_ED _BV(4)
520
522 #define TRX_IRQ_AMI _BV(5)
523
525 #define TRX_IRQ_UR _BV(6)
526
528 #define TRX_IRQ_BAT_LOW _BV(7)
529
531 #define TRAC_SUCCESS (0)
532
533 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
534
535 #define TRAC_NO_ACK (5)
536
537
539 #define TRX_MIN_CHANNEL (0)
540
542 #define TRX_MAX_CHANNEL (10)
543
545 #define TRX_NB_CHANNELS (11)
546
552 #define TRX_SUPPORTED_CHANNELS (0x00007ffUL)
553
558 #define TRX_SUPPORTED_PAGES (42)
559 #define TRX_SUPPORTS_BAND_700 (1)
560 #define TRX_SUPPORTS_BAND_800 (1)
561 #define TRX_SUPPORTS_BAND_900 (1)
562
564 #define TRX_BPSK20 (0)
565
567 #define TRX_BPSK40 (4)
568
570 #define TRX_OQPSK100 (8)
571
573 #define TRX_OQPSK200 (9)
574
576 #define TRX_OQPSK400 (10)
577 #define TRX_OQPSK400_1 (11)
578
580 #define TRX_OQPSK250 (12)
581
583 #define TRX_OQPSK500 (13)
584
586 #define TRX_OQPSK1000 (14)
587 #define TRX_OQPSK1000_1 (15)
588
589 #define TRX_NONE (255)
590
591 #endif /* ifndef AT86RF212_H */
trx_regaddr_t
uint8_t trx_regaddr_t
Definition: transceiver.h:89
trx_regval_t
uint8_t trx_regval_t
Definition: transceiver.h:85
trx_ramaddr_t
uint8_t trx_ramaddr_t
Definition: transceiver.h:81