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atmega_rfa1.h
1 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/atmega_rfa1.txt */
2
3 /* Copyright (c) 2009 Axel Wachtler
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
8 are met:
9
10 * Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15 * Neither the name of the authors nor the names of its contributors
16 may be used to endorse or promote products derived from this software
17 without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE. */
30
31 /* $Id$ */
36 #ifndef ATMEGA_128RFA1_H
37 #define ATMEGA_128RFA1_H (1)
38
39 /* === Includes ============================================================== */
40 #include <stdint.h>
41 /* === Externals ============================================================= */
42
43 /* === Types ================================================================= */
44
45 typedef uint8_t trx_ramaddr_t;
46 typedef uint8_t trx_regval_t;
47 typedef uint8_t trx_regaddr_t;
48
49 /* === Macros ================================================================ */
51 #define RG_TRX_STATUS (0x1)
52
53 #define SR_CCA_DONE 0x1,0x80,7
54
55 #define SR_CCA_STATUS 0x1,0x40,6
56
57 #define SR_TRX_STATUS 0x1,0x1f,0
58
59 #define RG_TRX_STATE (0x2)
60
61 #define SR_TRAC_STATUS 0x2,0xe0,5
62
63 #define SR_TRX_CMD 0x2,0x1f,0
64
65 #define RG_TRX_CTRL_0 (0x3)
66
67 #define SR_PAD_IO 0x3,0xe0,5
68
69 #define SR_PAD_IO_CLKM 0x3,0x10,4
70 #ifndef CLKM_2mA
71 #define CLKM_2mA (0)
72 #endif /* CLKM_2mA */
73 #ifndef CLKM_4mA
74 #define CLKM_4mA (1)
75 #endif /* CLKM_4mA */
76 #ifndef CLKM_6mA
77 #define CLKM_6mA (2)
78 #endif /* CLKM_6mA */
79 #ifndef CLKM_8mA
80 #define CLKM_8mA (3)
81 #endif /* CLKM_8mA */
82
83 #define SR_CLKM_SHA_SEL 0x3,0x8,3
84
85 #define SR_CLKM_CTRL 0x3,0x7,0
86 #ifndef CLKM_no_clock
87 #define CLKM_no_clock (0)
88 #endif /* CLKM_no_clock */
89 #ifndef CLKM_1MHz
90 #define CLKM_1MHz (1)
91 #endif /* CLKM_1MHz */
92 #ifndef CLKM_2MHz
93 #define CLKM_2MHz (2)
94 #endif /* CLKM_2MHz */
95 #ifndef CLKM_4MHz
96 #define CLKM_4MHz (3)
97 #endif /* CLKM_4MHz */
98 #ifndef CLKM_8MHz
99 #define CLKM_8MHz (4)
100 #endif /* CLKM_8MHz */
101 #ifndef CLKM_16MHz
102 #define CLKM_16MHz (5)
103 #endif /* CLKM_16MHz */
104
105 #define RG_TRX_CTRL_1 (0x4)
106
107 #define SR_PA_EXT_EN 0x4,0x80,7
108
109 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
110
111 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
112
113 #define SR_RX_BL_CTRL 0x4,0x10,4
114
115 #define SR_SPI_CMD_MODE 0x4,0xc,2
116
117 #define SR_IRQ_POLARITY 0x4,0x1,0
118
119 #define SR_IRQ_MASK_MODE 0x4,0x2,1
120
121 #define RG_PHY_TX_PWR (0x5)
122
123 #define SR_PA_BUF_LT 0x5,0xc0,6
124
125 #define SR_PA_LT 0x5,0x30,4
126
127 #define SR_TX_PWR 0x5,0xf,0
128
129 #define RG_PHY_RSSI (0x6)
130
131 #define SR_RX_CRC_VALID 0x6,0x80,7
132
133 #define SR_RND_VALUE 0x6,0x60,5
134
135 #define SR_RSSI 0x6,0x1f,0
136
137 #define RG_PHY_ED_LEVEL (0x7)
138
139 #define SR_ED_LEVEL 0x7,0xff,0
140
141 #define RG_PHY_CC_CCA (0x8)
142
143 #define SR_CCA_REQUEST 0x8,0x80,7
144
145 #define SR_CCA_MODE 0x8,0x60,5
146
147 #define SR_CHANNEL 0x8,0x1f,0
148
149 #define RG_CCA_THRES (0x9)
150
151 #define SR_CCA_ED_THRES 0x9,0xf,0
152
153 #define RG_RX_CTRL (0xa)
154
155 #define SR_PDT_THRES 0xa,0xf,0
156
157 #define RG_SFD_VALUE (0xb)
158
159 #define SR_SFD_VALUE 0xb,0xff,0
160
161 #define RG_TRX_CTRL_2 (0xc)
162
163 #define SR_RX_SAFE_MODE 0xc,0x80,7
164
165 #define SR_OQPSK_DATA_RATE 0xc,0x3,0
166
167 #define RG_ANT_DIV (0xd)
168
169 #define SR_ANT_SEL 0xd,0x80,7
170
171 #define SR_ANT_DIV_EN 0xd,0x8,3
172
173 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
174
175 #define SR_ANT_CTRL 0xd,0x3,0
176
177 #define RG_IRQ_MASK (0xe)
178
179 #define SR_MASK_BAT_LOW 0xe,0x80,7
180
181 #define SR_MASK_TRX_UR 0xe,0x40,6
182
183 #define SR_MASK_AMI 0xe,0x20,5
184
185 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
186
187 #define SR_MASK_TRX_END 0xe,0x8,3
188
189 #define SR_MASK_TRX_START 0xe,0x4,2
190
191 #define SR_MASK_PLL_LOCK 0xe,0x1,0
192
193 #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
194
195 #define RG_IRQ_STATUS (0xf)
196
197 #define SR_BAT_LOW 0xf,0x80,7
198
199 #define SR_TRX_UR 0xf,0x40,6
200
201 #define SR_AMI 0xf,0x20,5
202
203 #define SR_CCA_ED_READY 0xf,0x10,4
204
205 #define SR_RX_END 0xf,0x8,3
206
207 #define SR_RX_START 0xf,0x4,2
208
209 #define SR_PLL_LOCK 0xf,0x1,0
210
211 #define SR_PLL_UNLOCK 0xf,0x2,1
212
213 #define RG_VREG_CTRL (0x10)
214
215 #define SR_AVREG_EXT 0x10,0x80,7
216
217 #define SR_AVDD_OK 0x10,0x40,6
218
219 #define SR_DVREG_EXT 0x10,0x8,3
220
221 #define SR_DVDD_OK 0x10,0x4,2
222
223 #define RG_BATMON (0x11)
224
225 #define SR_BATMON_OK 0x11,0x20,5
226
227 #define SR_BATMON_HR 0x11,0x10,4
228
229 #define SR_BATMON_VTH 0x11,0xf,0
230
231 #define RG_XOSC_CTRL (0x12)
232
233 #define SR_XTAL_MODE 0x12,0xf0,4
234
235 #define SR_XTAL_TRIM 0x12,0xf,0
236
237 #define RG_RX_SYN (0x15)
238
239 #define SR_RX_PDT_DIS 0x15,0x80,7
240
241 #define SR_RX_PDT_LEVEL 0x15,0xf,0
242
243 #define RG_XAH_CTRL_1 (0x17)
244
245 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
246
247 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
248
249 #define SR_AACK_ACK_TIME 0x17,0x4,2
250
251 #define SR_AACK_PROM_MODE 0x17,0x2,1
252
253 #define RG_FTN_CTRL (0x18)
254
255 #define SR_FTN_START 0x18,0x80,7
256
257 #define RG_PLL_CF (0x1a)
258
259 #define SR_PLL_CF_START 0x1a,0x80,7
260
261 #define RG_PLL_DCU (0x1b)
262
263 #define SR_PLL_DCU_START 0x1b,0x80,7
264
265 #define RG_PART_NUM (0x1c)
266
267 #define SR_PART_NUM 0x1c,0xff,0
268 #ifndef RFA1_PART_NUM
269 #define RFA1_PART_NUM (131)
270 #endif /* RFA1_PART_NUM */
271
272 #define RG_VERSION_NUM (0x1d)
273
274 #define SR_VERSION_NUM 0x1d,0xff,0
275 #ifndef RFA1_VERSION_NUM_NONE
276 #define RFA1_VERSION_NUM_NONE (0)
277 #endif /* RFA1_VERSION_NUM_NONE */
278 #ifndef RFA1_VERSION_NUM_A
279 #define RFA1_VERSION_NUM_A (2)
280 #endif /* RFA1_VERSION_NUM_A */
281 #ifndef RFA1_VERSION_NUM_B
282 #define RFA1_VERSION_NUM_B (2)
283 #endif /* RFA1_VERSION_NUM_B */
284 #ifndef RFA1_VERSION_NUM_C
285 #define RFA1_VERSION_NUM_C (3)
286 #endif /* RFA1_VERSION_NUM_C */
287 #ifndef RFA1_VERSION_NUM_D
288 #define RFA1_VERSION_NUM_D (4)
289 #endif /* RFA1_VERSION_NUM_D */
290
291 #define RG_MAN_ID_0 (0x1e)
292
293 #define SR_MAN_ID_0 0x1e,0xff,0
294
295 #define RG_MAN_ID_1 (0x1f)
296
297 #define SR_MAN_ID_1 0x1f,0xff,0
298
299 #define RG_SHORT_ADDR_0 (0x20)
300
301 #define SR_SHORT_ADDR_0 0x20,0xff,0
302
303 #define RG_SHORT_ADDR_1 (0x21)
304
305 #define SR_SHORT_ADDR_1 0x21,0xff,0
306
307 #define RG_PAN_ID_0 (0x22)
308
309 #define SR_PAN_ID_0 0x22,0xff,0
310
311 #define RG_PAN_ID_1 (0x23)
312
313 #define SR_PAN_ID_1 0x23,0xff,0
314
315 #define RG_IEEE_ADDR_0 (0x24)
316
317 #define SR_IEEE_ADDR_0 0x24,0xff,0
318
319 #define RG_IEEE_ADDR_1 (0x25)
320
321 #define SR_IEEE_ADDR_1 0x25,0xff,0
322
323 #define RG_IEEE_ADDR_2 (0x26)
324
325 #define SR_IEEE_ADDR_2 0x26,0xff,0
326
327 #define RG_IEEE_ADDR_3 (0x27)
328
329 #define SR_IEEE_ADDR_3 0x27,0xff,0
330
331 #define RG_IEEE_ADDR_4 (0x28)
332
333 #define SR_IEEE_ADDR_4 0x28,0xff,0
334
335 #define RG_IEEE_ADDR_5 (0x29)
336
337 #define SR_IEEE_ADDR_5 0x29,0xff,0
338
339 #define RG_IEEE_ADDR_6 (0x2a)
340
341 #define SR_IEEE_ADDR_6 0x2a,0xff,0
342
343 #define RG_IEEE_ADDR_7 (0x2b)
344
345 #define SR_IEEE_ADDR_7 0x2b,0xff,0
346
347 #define RG_XAH_CTRL_0 (0x2c)
348
349 #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
350
351 #define SR_SLOTTED_OPERATION 0x2c,0x1,0
352
353 #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
354
355 #define RG_CSMA_SEED_0 (0x2d)
356
357 #define SR_CSMA_SEED_0 0x2d,0xff,0
358
359 #define RG_CSMA_SEED_1 (0x2e)
360
361 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
362
363 #define SR_AACK_SET_PD 0x2e,0x20,5
364
365 #define SR_AACK_DIS_ACK 0x2e,0x10,4
366
367 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
368
369 #define SR_CSMA_SEED_1 0x2e,0x7,0
370
371 #define RG_CSMA_BE (0x2f)
372
373 #define SR_MAX_BE 0x2f,0xf0,4
374
375 #define SR_MIN_BE 0x2f,0xf,0
376
377 #define RADIO_NAME "ATmega128RFA1"
378
379 #define RADIO_PART_NUM (RFA1_PART_NUM)
380
381 #if RADIO_TYPE == RADIO_ATMEGA128RFA1_A
382 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_A)
383 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_B
384 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_B)
385 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_C
386 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_C)
387 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_D
388 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_D)
389 #endif
390
391
393 #define TRX_REGISTER_BASEADDR (0x140)
394
395 #define AES_REGISTER_BASEADDR (0x13c)
396
397
398 #define TRX_IF_RFA1 (1) /* interfaces to RFA1 rather than SPI */
399
400 #define TRX_CMD_RADDR_MASK (0x3f)
401
403 #define TRX_RESET_TIME_US (6)
404
406 #define TRX_INIT_TIME_US (510)
407
409 #define TRX_PLL_LOCK_TIME_US (180)
410
411
413 #define TRX_CCA_TIME_US (140)
414
416 #define TRX_IRQ_PLL_LOCK _BV(0)
417
419 #define TRX_IRQ_PLL_UNLOCK _BV(1)
420
422 #define TRX_IRQ_RX_START _BV(2)
423
425 #define TRX_IRQ_RX_END _BV(3)
426
428 #define TRX_IRQ_CCA_ED _BV(4)
429
431 #define TRX_IRQ_AMI _BV(5)
432
434 #define TRX_IRQ_TX_END _BV(6)
435
437 #define TRX_MIN_CHANNEL (11)
438
440 #define TRX_MAX_CHANNEL (26)
441
443 #define TRX_NB_CHANNELS (16)
444
449 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
450
451 #define TRX_SUPPORTS_BAND_2400 (1)
452
456 #define TRX_SUPPORTED_PAGES (42)
457
459 #define TRX_OQPSK250 (0)
460
462 #define TRX_OQPSK500 (1)
463
465 #define TRX_OQPSK1000 (2)
466
467 #define TRX_OQPSK2000 (3)
468
469 #define TRX_NONE (255)
470
471 #ifdef __cplusplus
472 extern "C" {
473 #endif
474
475 extern volatile uint8_t SHADOW_IRQ_MASK;
476 static inline void disable_all_trx_irqs(void)
477 {
478 SHADOW_IRQ_MASK = IRQ_MASK;
479 IRQ_MASK = 0;
480 }
481
482 static inline void enable_all_trx_irqs(void)
483 {
484 static bool already_shadowed = 0;
485 if (already_shadowed == 0)
486 {
487 /* enable_all_trx_irqs was never called before */
488 SHADOW_IRQ_MASK = IRQ_MASK;
489 already_shadowed = 1;
490 }
491 else
492 {
493 if (IRQ_MASK != 0)
494 {
495 /* mask register was modified by direct access */
496 SHADOW_IRQ_MASK = IRQ_MASK;
497 }
498 else
499 {
500 /* restore last registervalue */
501 IRQ_MASK = SHADOW_IRQ_MASK;
502 }
503 }
504 }
505
506 #ifdef __cplusplus
507 } /* extern "C" */
508 #endif
509
510 #endif /* ifndef ATMEGA_128RFA1_H */
trx_regaddr_t
uint8_t trx_regaddr_t
Definition: transceiver.h:89
trx_regval_t
uint8_t trx_regval_t
Definition: transceiver.h:85
trx_ramaddr_t
uint8_t trx_ramaddr_t
Definition: transceiver.h:81