base_zdma1281.h

    00001 /* Copyright (c) 2008 Axel Wachtler
    00002    All rights reserved.
    00003
    00004    Redistribution and use in source and binary forms, with or without
    00005    modification, are permitted provided that the following conditions
    00006    are met:
    00007
    00008    * Redistributions of source code must retain the above copyright
    00009      notice, this list of conditions and the following disclaimer.
    00010    * Redistributions in binary form must reproduce the above copyright
    00011      notice, this list of conditions and the following disclaimer in the
    00012      documentation and/or other materials provided with the distribution.
    00013    * Neither the name of the authors nor the names of its contributors
    00014      may be used to endorse or promote products derived from this software
    00015      without specific prior written permission.
    00016
    00017    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    00018    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    00019    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    00020    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
    00021    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    00022    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    00023    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    00024    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    00025    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    00026    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    00027    POSSIBILITY OF SUCH DAMAGE. */
    00028
    00029 /* $Id$ */
    00030
    00031 /* Basic configuration for Meshnetics ZigBits ZDM-A1281-(P1,A2,E1,Amp)
    00032  * For wiring details see http://www.mikrocontroller.net/articles/Meshnetics_Zigbee
    00033  */
    00034
    00035 #ifndef BASE_ZDMA1281_H
    00036 #define BASE_ZDMA1281_H
    00037
    00038 #ifndef PB0
    00039 # define PB0 (0)
    00040 # define PB1 (1)
    00041 # define PB2 (2)
    00042 # define PB3 (3)
    00043 # define PB4 (4)
    00044 # define PB5 (5)
    00045 # define PB6 (6)
    00046 # define PB7 (7)
    00047 # define PD4 (4)
    00048 #endif
    00049
    00050 #ifndef DEFAULT_SPI_RATE
    00051 # define DEFAULT_SPI_RATE  (SPI_RATE_1_2)
    00052 #endif
    00053
    00054 /*=== Hardware Components ============================================*/
    00055
    00056 #ifndef RADIO_TYPE
    00057 #define RADIO_TYPE (RADIO_AT86RF230)
    00058 #endif
    00059 /*=== TRX pin access macros ==========================================*/
    00060
    00061 #define DDR_TRX_RESET   DDRA
    00062 #define PORT_TRX_RESET  PORTA
    00063 #define MASK_TRX_RESET  (_BV(7))
    00066 #define TRX_RESET_INIT() DDR_TRX_RESET |= MASK_TRX_RESET
    00067
    00068 #define TRX_RESET_HIGH() PORT_TRX_RESET |= MASK_TRX_RESET
    00069
    00070 #define TRX_RESET_LOW()  PORT_TRX_RESET &= ~MASK_TRX_RESET
    00071
    00073 #define PORT_TRX_SLPTR  PORTB
    00074
    00075 #define DDR_TRX_SLPTR   DDRB
    00076
    00077 #define MASK_TRX_SLPTR  (_BV(PB4))
    00078
    00080 #define TRX_SLPTR_INIT() DDR_TRX_SLPTR |= MASK_TRX_SLPTR
    00081
    00082 #define TRX_SLPTR_HIGH() PORT_TRX_SLPTR |= MASK_TRX_SLPTR
    00083
    00084 #define TRX_SLPTR_LOW()  PORT_TRX_SLPTR &= ~MASK_TRX_SLPTR
    00085
    00086
    00087 /*=== IRQ access macros ==============================================*/
    00090 # define TRX_IRQ         _BV(INT5)
    00091 # define TRX_IRQ_vect    INT5_vect
    00092
    00097 # define TRX_IRQ_INIT()  do{\
    00098                             EICRB  |= (_BV(ISC51)|_BV(ISC50));\
    00099                             EIFR =TRX_IRQ; \
    00100                           } while(0)
    00101
    00103 #define DI_TRX_IRQ() {EIMSK &= ~TRX_IRQ;}
    00104
    00106 #define EI_TRX_IRQ() {EIMSK |= TRX_IRQ;}
    00107
    00109 #define TRX_TSTAMP_REG TCNT1
    00110
    00111 /*=== SPI access macros ==============================================*/
    00112 #define DDR_SPI  (DDRB)
    00113 #define PORT_SPI (PORTB)
    00115 #define SPI_MOSI _BV(PB2)
    00116 #define SPI_MISO _BV(PB3)
    00117 #define SPI_SCK  _BV(PB1)
    00118 #define SPI_SS   _BV(PB0)
    00120 #define SPI_DATA_REG SPDR
    00126 static inline void SPI_INIT(uint8_t spirate)
    00127 {
    00128     /* first configure SPI Port, then SPCR */
    00129     PORT_SPI |= SPI_SCK | SPI_SS;
    00130     DDR_SPI  |= SPI_MOSI | SPI_SCK | SPI_SS;
    00131     DDR_SPI  &= ~SPI_MISO;
    00132
    00133     SPCR = (_BV(SPE) | _BV(MSTR));
    00134
    00135     SPCR &= ~(_BV(SPR1) | _BV(SPR0) );
    00136     SPSR &= ~_BV(SPI2X);
    00137
    00138     SPCR |= (spirate & 0x03);
    00139     SPSR |= ((spirate >> 2) & 0x01);
    00140
    00141 }
    00142
    00144 #define SPI_SELN_LOW()       uint8_t sreg = SREG; cli(); PORT_SPI &=~SPI_SS
    00145
    00146 #define SPI_SELN_HIGH()      PORT_SPI |= SPI_SS; SREG = sreg
    00147
    00148 #define SPI_WAITFOR()        do { while((SPSR & _BV(SPIF)) == 0);} while(0)
    00149
    00150
    00151 #endif
    00152 /* EOF */